AS3711
Quad Buck High Current PMIC with
Charger
General Description
The AS3711 is a compact System PMU with integrated battery
charger and back light driver.
The device offers advanced power management functions. All
necessary ICs and peripherals in a battery powered mobile
device are supplied by the AS3711. It features 3 DCDC buck
converters as well as 8 low noise LDOs. The different regulated
supply voltages are programmable via the serial control
interface. 4MHz operation with 1uH coils are reducing cost and
PCB space.
AS3711 further features a DCDC buck controller which is ideal
to support processor core currents up to 3A.
The two step-up converter generate voltages for e.g.the
backlight, classD amplifier, USB host support or LCD display
supply. Both constant voltage (for e.g. OLED supply) as well as
constant current (white LED backlight) operations with three
current sinks are possible. An internal voltage protection is
limiting the output voltage in the case of external component
failures.
AS3711 contains a linear or switching mode Li-Ion battery
charger with constant current and constant voltage. The
maximum charging current is 1.5A. An integrated battery
switch and an optional external switch are separating the
battery during charging or whenever an external power supply
is present. With this switch it is also possible to operate with no
or deeply discharged batteries. A programmable current limit
(100mA - 2.5A) can be used to control the maximum current
used from a USB supply or charger input. Additional features
are a 30V OV protection and battery temperature supervision.
The single supply voltage may vary from 2.7V to 5.5V.
Ordering Information and Content Guide appear at end of
datasheet.
ams Datasheet
[v1-34] 2014-Nov-10
Page 1
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AS3711 − General Description
Key Benefits & Features
The benefits and features of AS3711, Quad Buck High Current
PMIC with Charger are listed below:
Figure 1:
Added Value Of Using AS3711
Benefits
Features
Compact design due to small coils for IO
and memory voltage generation
• 3 DCDC step down regulators (2-4MHz)
- DVM (0.6V-3.3V;1×1.2-1.5A, 2×0.7-1A)
- 60μA quiescent current
- 2A with combined DCDC 2 & 3
High current generation for processor core
• DCDC step down controller
- DVM (0.6V-3.3V; 2-3A)
Supply multiple independent voltage rails
for general IO supplies
• 2 analog low noise LDOs, 6 digital LDOs
- 2×1.2-3-3V, 6×0.9-3.3V; 150-300mA
- 30μA quiescent current (low power mode)
• 1 ultra low power always on LDO 2.5V, 10mA
Backlight boost controller for multiple
display configurations or fixed voltage
supplies
HV Backlight Driver
• 2×step up with external transistor
- e.g. 0.5-1A@5V; 40mA@50V
• Voltage control mode and over-voltage protection
• 3 programmable current sinks (max. 40mA)
• Possible external PWM dimming input (DLS, CABC)
Self contained free configurable charger
with stand alone supervisory functions
Battery Charger
• Programmable trickle charging (25-220mA)
• Programmable constant current charging (up to 1500mA)
• Programmable constant voltage charging (3.9V-4.25V)
• Charger time-out and temperature supervision
• Selectable current limitation for USB mode
• Integrated battery switch & ideal diode (linear mode)
• External battery switch control (switching mode)
• External 30V OV protection
Save supervision in HV which works also
without a processor
Supervisor
• Automatic battery monitoring with interrupt generation
and selectable warning level
• Automatic temperature monitoring with interrupt
generation and selectable warning and shutdown levels
Very low current time keeping and alarm
functions without the need of a processor
Real Time Clock
• Ultra low power 32kHz oscillator
• Sec and minute counter, auto wake-up
• Programmable alarm
• Repeating alarm (seconds, minutes, 2 minutes,
or 8 minutes)
• 32kHz clock output to peripheral
• 0
0 : No GPIO control
1 : Controlled by GPIO1
2 : Controlled by GPIO2
3 : Controlled by GPIO3
RW
Enable GPIO control of DCDC SD3. GPIO ctrl only
enabled, if sd3_vsel > 0
0 : No GPIO control
1 : Controlled by GPIO1
2 : Controlled by GPIO2
3 : Controlled by GPIO3
RW
Enable GPIO control of DCDC SD2. GPIO ctrl only
enabled, if sd2_vsel > 0
0 : No GPIO control
1 : Controlled by GPIO1
2 : Controlled by GPIO2
3 : Controlled by GPIO3
RW
Enable GPIO control of DCDC SD1. GPIO ctrl only
enabled, if sd1_vsel > 0
0 : No GPIO control
1 : Controlled by GPIO1
2 : Controlled by GPIO2
3 : Controlled by GPIO3
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 96:
GPIOctrl_ldo1 Register (Address 26h)
Addr: 26h
Bit
7:6
5:4
3:2
1:0
Bit Name
gpio_ctrl_ldo4
gpio_ctrl_ldo3
gpio_ctrl_ldo2
gpio_ctrl_ldo1
ams Datasheet
[v1-34] 2014-Nov-10
GPIOctrl_ldo1
Default
'b00
'b00
'b00
'b00
Access
Bit Description
RW
Enable GPIO control of LDO4. GPIO ctrl only enabled, if
ldo4_on = 1
0 : No GPIO control
1 : Controlled by GPIO1
2 : Controlled by GPIO2
3 : Controlled by GPIO3
RW
Enable GPIO control of LDO3. GPIO ctrl only enabled, if
ldo3_on = 1
0 : No GPIO control
1 : Controlled by GPIO1
2 : Controlled by GPIO2
3 : Controlled by GPIO3
RW
Enable GPIO control of LDO2. GPIO ctrl only enabled, if
ldo2_on = 1
0 : No GPIO control
1 : Controlled by GPIO1
2 : Controlled by GPIO2
3 : Controlled by GPIO3
RW
Enable GPIO control of LDO1. GPIO ctrl only enabled, if
ldo1_on = 1
0 : No GPIO control
1 : Controlled by GPIO1
2 : Controlled by GPIO2
3 : Controlled by GPIO3
Page 93
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AS3711 − Register Over view
Figure 97:
GPIOctrl_ldo2 Register (Address 27h)
Addr: 27h
Bit
7:6
5:4
3:2
1:0
Bit Name
gpio_ctrl_ldo8
gpio_ctrl_ldo7
gpio_ctrl_ldo6
gpio_ctrl_ldo5
Page 94
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GPIOctrl_ldo2
Default
'b00
'b00
'b00
'b00
Access
Bit Description
RW
Enable GPIO control of LDO8. GPIO ctrl only enabled, if
ldo8_on = 1
0 : No GPIO control
1 : Controlled by GPIO1
2 : Controlled by GPIO2
3 : Controlled by GPIO3
RW
Enable GPIO control of LDO7. GPIO ctrl only enabled, if
ldo7_on = 1
0 : No GPIO control
1 : Controlled by GPIO1
2 : Controlled by GPIO2
3 : Controlled by GPIO3
RW
Enable GPIO control of LDO6. GPIO ctrl only enabled, if
ldo6_on = 1
0 : No GPIO control
1 : Controlled by GPIO1
2 : Controlled by GPIO2
3 : Controlled by GPIO3
RW
Enable GPIO control of LDO5. GPIO ctrl only enabled, if
ldo5_on = 1
0 : No GPIO control
1 : Controlled by GPIO1
2 : Controlled by GPIO2
3 : Controlled by GPIO3
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 98:
Reg3_Voltage Register (Address 2bh)
Addr: 2bh
Bit
7:0
Bit Name
reg3_voltage
Reg3_Voltage
Default
'b0000 0000
Access
Bit Description
RW
This register is mapped to the register address
0h+Reg3_select , if gioX_iosf=5 or 6 (Vselect input), and
GPIOx input = 1, This feature allows voltage switching of
a predefined regulator with just one GPIO input
0 ..FFh : Selects voltage, ilimit, on or frequency bits of
LDO or DCDC
Bit Description
Figure 99:
Reg_control3 Register (Address 2ch)
Addr: 2ch
Reg3_Voltage
Bit
Bit Name
Default
Access
7:4
-
'b0000
n/a
Do not use
3:0
reg3_select
'b1111
RW
Selects regulator for mapping feature; if reg_select3 ≥
0Ch, then feature is disabled.
ams Datasheet
[v1-34] 2014-Nov-10
Page 95
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AS3711 − Register Over view
Figure 100:
SD_control1 Register (Address 30h)
Addr: 30h
Bit
7
6
5
4
3
2
1
0
Bit Name
sd4_low_noise
sd3_low_noise
sd2_low_noise
sd1_low_noise
sd4_fast
sd3_fast
sd2_fast
sd1_fast
Page 96
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SD_control1
Default
0
0
0
0
0
0
0
0
Access
Bit Description
RW
Enables low noise mode of SD4. If enabled, smaller current
pulses and output ripple is activated.
0 : Normal mode. Minimum current pulses of >100mA
applied in skip mode.
1 : Low noise mode. Only minimum on time applied in
skip mode.
RW
Enables low noise mode of SD3. If enabled, smaller current
pulses and output ripple is activated.
0 : Normal mode. Minimum current pulses of >100mA
applied in skip mode.
1 : Low noise mode. Only minimum on time applied in
skip mode.
RW
Enables low noise mode of SD2. If enabled, smaller current
pulses and output ripple is activated.
0 : Normal mode. Minimum current pulses of >100mA
applied in skip mode.
1 : Low noise mode. Only minimum on time applied in
skip mode.
RW
Enables low noise mode of SD1. If enabled, smaller current
pulses and output ripple is activated.
0 : Normal mode. Minimum current pulses of >100mA
applied in skip mode.
1 : Low noise mode. Only minimum on time applied in
skip mode.
RW
Selects a faster regulation mode for SD4 suitable for larger
load changes.
0 : Normal mode
1 : Fast mode, double Cext required (see external
components)
RW
Selects a faster regulation mode for SD3 suitable for larger
load changes.
0 : Normal mode
1 : Fast mode, double Cext required (see external
components)
RW
Selects a faster regulation mode for SD2 suitable for larger
load changes.
0 : Normal mode
1 : Fast mode, double Cext required (see external
components)
RW
Selects a faster regulation mode for SD1 suitable for larger
load changes.
0 : Normal mode
1 : Fast mode, double Cext required (see external
components)
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 101:
SD_control2 Register (Address 31h)
Addr: 31h
Bit
7:6
Bit Name
sd_dvm_select
SD_control2
Default
'b00
Access
Bit Description
RW
Apply DVM counter to the following DCDC converter:
0 : Select SD1 for DVM
1 : Select SD2 for DVM
2 : Select SD3 for DVM
3 : Select SD4 for DVM
5:4
dvm_time
'b00
RW
Time steps of DVM voltage change of selected step
down, if voltage of step Down is changed during
operation (sdx_vsel) voltage is decreased/increased by
single steps 12.5mV
0 : 0 μsec, immediate change (no DVM)
1 : 4 μsec time delay between steps
2 : 8 μsec time delay between steps
3 : 16 μsec time delay between steps
3
sd3_slave
0
RW
Enables slave mode of SD3
0 : Normal mode of SD3
1 : SD3 is slave of SD2
2
sd3_fsel
0
RW
Selects between high and low frequency range
0 : 2 or 3MHz frequency (selectable by sd3_frequ)
1 : 3 or 4MHz frequency (selectable by sd3_frequ)
1
sd2_fsel
0
RW
Selects between high and low frequency range
0 : 2 or 3MHz frequency (selectable by sd2_frequ)
1 : 3 or 4MHz frequency (selectable by sd2_frequ)
0
sd1_fsel
0
RW
Selects between high and low frequency range
0 : 2 or 3MHz frequency (selectable by sd1_frequ)
1 : 3 or 4MHz frequency (selectable by sd1_frequ)
ams Datasheet
[v1-34] 2014-Nov-10
Page 97
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AS3711 − Register Over view
Figure 102:
Battery_voltage_monitor Register (Address 32h)
Addr: 32h
Battery_voltage_monitor
Bit
Bit Name
Default
Access
7
FastResEn
0
RW
0 : ResVoltFall debounce time = 3msec
1 : ResVoltFall debounce time = 49sec
RW
0 : A reset is generated if VSUP falls below 2.7V **
1 : A reset is generated if VSUP falls below ResVoltFall
** If VBAT falls below ResVoltFall only an interrupt is
generated (if enabled) and the μProcessor can shut
down the system)
RW
This value determines the reset level ResVoltFall for
falling VBAT. It is recommended to set this value at least
200mV lower than ResVoltRise
0 : 2.7V
1 : 2.9V
2 : 3.1V
3 : 3.2V
4 : 3.3V
5 : 3.4V
6 : 3.5V
7 : 3.6V
RO (OTP)
This value determines the reset level ResVoltRise for
rising VBAT. It is recommended to set this value at least
200mV higher than ResVoltFall
0 : 2.7V
1 : 2.9V
2 : 3.1V
3 : 3.2V
4 : 3.3V
5 : 3.4V
6 : 3.5V
7 : 3.6V
6
5:3
2:0
SupResEn
ResVoltFall
ResVoltRise
Page 98
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0
'b000
'b000
Bit Description
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 103:
Startup_Control Register (Address 33h)
Addr: 33h
Startup_Control
Bit
Bit Name
Default
Access
7:2
-
‘b00 0000
n/a
1
0
chg_pwr_off_en
power_off_at_vsupl
ow
ams Datasheet
[v1-34] 2014-Nov-10
0
0
RO (OTP)
RW
Bit Description
Do not use
Select charger detection in power OFF mode Read
only (OTP setting)
0 : Exit of Power OFF mode, if charger is detected
(level detection)
1 : Exit of Power OFF mode, if charger insertion is
detected (rising edge detection) .
Switch ON Power OFF mode if low VSUP is detected
during active or standby mode (Pin ON= low and bit
auto_off=0)
0 : If low battery is detected, battery voltage is
continuously monitored and chip startup initiated if
battery voltage is above ResVoltRise
1 : If low battery is detected, enter power OFF mode
Page 99
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AS3711 − Register Over view
Figure 104:
ResetTimer Register (Address 34h)
Addr: 34h
ResetTimer
Bit
Bit Name
Default
Access
7
-
'b0
n/a
Do not use
RW
Disable Reset output signal (pin XRES) in standby
mode.
0 : Normal mode, reset is active in standby mode
1 : No reset in standby mode and during exit of
standy mode
RO
Defines startup behavior at first battery insertion
0 : Startup of chip if VBAT>ResVoltRise
1 : Enter power OFF mode (Startup with ON key or
charger insertion)
6
5
stby_reset_disable
auto_off
0
0
Bit Description
4:3
off_delay
'b01
RW
Set Delay between I²C command, GPIO or Reset signal
for power_off, standby mode or reset and execution
of that command.
0 : No delay
1 : 8 msec
2 : 16 msec
3 : 32 msec
2
-
'b0
n/a
Do not use
RW
Set RESTime, after the last regulator has started
0 : RESTIME = 10ms
1 : RESTIME = 50ms
2 : RESTIME = 100ms
3 : RESTIME = 150ms
1:0
res_timer
Page 100
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'b00
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 105:
ReferenceControl Register (Address 35h)
Addr: 35h
ReferenceControl
Bit
Bit Name
Default
Access
7
on_reset_delay
0
RW
Sets the ON reset delay time
0 : 8 sec (if onkey_reset=1)
1 : 4 sec (if onkey_reset=1)
6
reg_low_bias_mode
0
RW
Sets the ON reset delay time
0 : Normal operation
1 : Reduces the bias for the analog LDO1 and LDO2
RW
Divide internal clock oscillator by 2 to reduce
quiescent current for low power operation
0 : Normal mode
1 : Internal clock frequency divided by two. All
timings are increased by two. Switching frequency of
all DCDC converters are divided by two. Reduced
transient performance of DCDC converters.
RW
Setting to 1 sets the PMU into standby mode. All
regulators are disabled except those regulators
enabled by register Reg standby mode. XRES will be
pulled to low. A normal startup of all regulators will
be done with any interrupt (has to be enabled before
entering standby mode). During this startup,
regulators defined by Reg standby mode register are
continuously ON.
RW
Sets the internal CLK frequency fCLK used for DCDCs,
PWM, ...
0 : 4 MHz (default)
1 : 3.8 MHz
2 : 3.6 MHz
3 : 3.4 MHz
4 : 3.2 MHz
5 : 3.0 MHz
6 : 2.8 MHz
7 : 2.6 MHz All frequencies, timings and delays in this
datasheet are based on 4MHz clk_int
RW
Enable low power mode of internal reference.
0 : Standard mode
1 : Low power mode -all specification except noise
parameters are still valid. Iq reduced by approx. 30μA
5
4
3:1
0
clk_div2
standby_mode_on
clk_int
low_power_on
ams Datasheet
[v1-34] 2014-Nov-10
0
0
'b000
0
Bit Description
Page 101
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AS3711 − Register Over view
Figure 106:
ResetControl Register (Address 36h)
Addr: 36h
ResetControl
Bit
Bit Name
Default
Access
7
onkey_reset
0
RW
0 : Reset after 4/8 seconds ON pressed disabled
1 : Reset after 4/8 seconds ON pressed enabled
RW
Flags to indicate to the software the reason for the
last reset
0 : VPOR has been reached (battery or charger
insertion from scratch)
1 : ResVoltFall was reached (battery voltage drop
below 2.75V)
2 : Software forced by force_reset
3 : Software forced by power_off and ON was pulled
high
4 : Software forced by power_off and charger was
detected
5 : External triggered through the pin XRES
6 : Reset caused by overtemperature T140
7 : Reset caused by watchdog
8 : Reset caused by 4/8 seconds ON press
9 : NA
10 : Reset caused by RTC repeated wakeup or alarm
wakeup
11 : Reset caused by interrupt in standby mode
12 : Reset caused by ON pulled high in standby mode
6:3
reset_reason
'b0000
Bit Description
Read: This flag represents the state of the ON pad
directly
Write: Setting to 1 resets the 4/8 sec. onkey_reset
timer
2
on_input
0
R_PUSH
1
power_off
0
RW
Setting to 1 starts a reset cycle, but waits after the
Reg_off state for a rising edge on the pin ON or until
the charger is detected.
0
force_reset
0
RW
Setting to 1 starts a complete reset cycle
Page 102
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ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 107:
OvertemperatureControl Register (Address 37h)
Addr: 37h
OvertemperatureControl
Bit
Bit Name
Default
Access
7:4
-
'b0000
n/a
Do not use
RW
If the over-temperature threshold 2 has been
reached, the flag ov_temp_140 is set and a reset
cycle is started. ov_temp_140 should be reset by
writing 1 and afterward 0 to rst_ov_temp_140.
3
rst_ov_temp_140
0
Bit Description
2
ov_temp_140
0
RO
Flag that the over-temperature threshold 2 (T140) has
been reached -this flag is not reset by a
over-temperature caused reset and has to be reset by
rst_ov_temp_140.
1
ov_temp_110
0
RO
Flag that the over-temperature threshold 1 (T110) has
been reached
0
temp_pmc_on
1
RO
Switch ON /OFF of temperature supervision; default:
ON -all other bits are only valid if set to 1. Leave at 1,
do not disable
Figure 108:
WatchdogControl Register (Address 38h)
Addr: 38h
WatchdogControl
Bit
Bit Name
Default
Access
7:2
-
'b00 0000
n/a
Do not use
1
wtdg_res_on
0
RW
If the watchdog expires and wtdg_res_on = 1 a reset
cycle will be started
0
wtdg_on
0
RW
Switches ON the complete watchdog
0 : Watchdog OFF
1 : Watchdog enabled
ams Datasheet
[v1-34] 2014-Nov-10
Bit Description
Page 103
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AS3711 − Register Over view
Figure 109:
Reg_standby_mod1 Register (Address 39h)
Addr: 39h
Bit
Bit Name
Reg_standby_mod1
Default
Access
Bit Description
7
disable_regpd
0
RW
This bit disables the pulldown of all regulators
0 : Normal operation approx. 1kΩ pulldown of all
regulators
1 : Pulldown disabled >100kΩ of all regulators
6:4
-
b000
n/a
Do not use
3
sd4_stby_on
0
RW
Enable Step down 4 in standby mode
2
sd3_stby_on
0
RW
Enable Step down 3 in standby mode
1
sd2_stby_on
0
RW
Enable Step down 2 in standby mode
0
sd1_stby_on
0
RW
Enable Step down 1 in standby mode
Figure 110:
Reg_standby_mod2 Register (Address 3ah)
Addr: 3ah
Reg_standby_mod2
Bit
Bit Name
Default
Access
7
ldo8_stby_on
0
RW
Enable LDO8 in standby mode
6
ldo7_stby_on
0
RW
Enable LDO7 in standby mode
5
ldo6_stby_on
0
RW
Enable LDO6 in standby mode
4
ldo5_stby_on
0
RW
Enable LDO5 in standby mode
3
ldo4_stby_on
0
RW
Enable LDO4 in standby mode
2
ldo3_stby_on
0
RW
Enable LDO3 in standby mode
1
ldo2_stby_on
0
RW
Enable LDO2 in standby mode
0
ldo1_stby_on
0
RW
Enable LDO1 in standby mode
Page 104
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Bit Description
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 111:
curr_control Register (Address 40h)
Addr: 40h
Bit
7:4
3:2
1:0
Bit Name
curr3_ctrl
curr2_ctrl
curr1_ctrl
ams Datasheet
[v1-34] 2014-Nov-10
curr_control
Default
'b0000
'b00
'b00
Access
Bit Description
RW
ON/OFF control of the pad CURR3
0 : Current sink is turned OFF
1 : Current sink is active
2 : Current sink is active and LED string connected to
SU2. Required for automatic feedback selection.
3 : Controlled by internal PWM generator, or external,
if gpioX_iosf=4
4 : XINT output (active low interrupt output)
5 : VSUP_low output
6 : Charger active output
7 : EOC output
8 : Inverted signal of ON pin as output
9 : Signal of ON pin as output
10: Q32k output (if rtc_on=0 then internal RC
oscillator with 32kHz divider is used)
11 : PWM output
12 : PWRGOOD output
13-15 : NA
RW
ON/OFF control of the pad CURR2
0 : Current sink is turned OFF
1 : Current sink is active
2 : Current sink is active and LED string connected to
SU2. Required for automatic feedback selection.
3 : Controlled by internal PWM generator, or external,
if gpioX_iosf=4
RW
ON/OFF control of the pad CURR1
0 : Current sink is turned OFF
1 : Current sink is active
2 : Current sink is active and LED string connected to
SU2. Required for automatic feedback selection.
3 : Controlled by internal PWM generator, or external,
if gpioX_iosf=4
Page 105
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AS3711 − Register Over view
Figure 112:
pwm_control_l Register (Address 41h)
Addr: 41h
Bit
7:0
Bit Name
pwm_l_time
pwm_control_l
Default
'b00000000
Access
Bit Description
RW
This bit defines the low time of the PWM generator in
1MHz units.
0 : pwm_div * 1μsec
1 : pwm_div * 2μsec
2 : pwm_div * 3μsec
... : ...
255 : pwm_div * 256μsec
Figure 113:
pwm_control_h Register (Address 42h)
Addr: 42h
Bit
7:0
Bit Name
pwm_h_time
pwm_control_h
Default
'b00000000
Access
RW
Bit Description
This bit defines the high time of the PWM generator
in 1MHz units.
0 : pwm_div * 1μsec
1 : pwm_div * 2μsec
2 : pwm_div * 3μsec
... : ...
255 : pwm_div * 256μsec
Figure 114:
curr1_value Register (Address 43h)
Addr: 43h
Bit
7:0
Bit Name
curr1_current
Page 106
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curr1_value
Default
'b00000000
Access
RW
Bit Description
Defines the current into CURR1, if enabled by
curr1_ctrl
0 : Power down (default state)
1 : 0.1563mA (LSB)
... : ...
255 : 39.84mA
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 115:
curr2_value Register (Address 44h)
Addr: 44h
Bit
7:0
Bit Name
curr2_current
curr2_value
Default
'b00000000
Access
RW
Bit Description
Defines the current into CURR2, if enabled by
curr2_ctrl
0 : Power down (default state)
1 : 0.1563mA (LSB)
... : ...
255 : 39.84mA
Figure 116:
curr3_value Register (Address 45h)
Addr: 45h
Bit
7:0
Bit Name
curr3_current
curr3_value
Default
'b00000000
Access
RW
Bit Description
Defines the current into CURR3, if enabled by
curr3_ctrl
0 : Power down (default state)
1 : 0.1563mA (LSB)
... : ...
255 : 39.84mA
Figure 117:
Watchdog_min_timer Register (Address 46h)
Addr: 46h
Watchdog_min_timer
Bit
Bit Name
Default
Access
7:0
wtdg_min_timer
'b00000000
RW
Bit Description
Defines the minimum watchdog trigger time
(LSB=7.5ms, range: 0 - 1.9s)
Figure 118:
Watchdog_max_timer Register (Address 47h)
Addr: 47h
Watchdog_max_timer
Bit
Bit Name
Default
Access
7:0
wtdg_max_timer
'b00000000
RW
ams Datasheet
[v1-34] 2014-Nov-10
Bit Description
Defines the maximum watchdog trigger time
(LSB=7.5ms, range: 7.5ms - 1.9s), do not set to (00)h
Page 107
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AS3711 − Register Over view
Figure 119:
WatchdogSoftwareSignal Register (Address 48h)
Addr: 48h
Bit
Bit Name
WatchdogSoftwareSignal
Default
Access
Bit Description
7:6
pwm_div
'b00
RW
This bit defines the divider ratio of the prescaler for
the PWM generator.
0 : Divide by 1
1 : Divide by 2
2 : Divide by 4
3 : Divide by 16
0
wtdg_sw_sig
0
PUSH
Trigger input by the serial interface if gpioX_iosf9
Figure 120:
Stepup_control1 Register (Address 50h)
Addr: 50h
Bit
7:3
Bit Name
stepup1_v
Stepup_control1
Default
'b0000
Access
Bit Description
RW
Defines the tuning current at FB_SU1 pin;
0 : 0 μA
1 : 1 μA
... : ...
31 : 31 μA
2
stepup1_res
0
RW
Gain selection for DCDC SU1
0 : If FB_SU1 is used with current feedback only (Only
R1,C1 connected)
1 : If FB_SU1 is used with external resistor divider (2
resistors)
1
stepup1_freq
0
RW
Selects SU1 frequency
0 : 1 MHz
1 : 0.5 MHz
0
stepup1_on
0
RW
ON/OFF control of SU1
0 : SU1 OFF
1 : SU1 ON
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[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 121:
Stepup_control2 Register (Address 51h)
Addr: 51h
Bit
7:3
Bit Name
stepup2_v
Stepup_control2
Default
'b0000
Access
Bit Description
RW
Defines the tuning current at FB_SU2 pin;
0 : 0 μA
1 : 1 μA
... : ...
31 : 31 μA
2
stepup2_res
0
RW
Gain selection for DCDC SU2
0 : If DCDC is used with current feedback
(CURR1,CURR2,CURR3) or if FB_SU2 is used with
current feedback only (Only R1,C1 connected)
1 : If FB_SU2 is used with external resistor divider (2
resistors)
1
stepup2_freq
0
RW
Selects SU3 frequency
0 : 1 MHz
1 : 0.5 MHz
0
stepup2_on
0
RW
ON/OFF control of SU2
0 : SU2 OFF
1 : SU2 ON
ams Datasheet
[v1-34] 2014-Nov-10
Page 109
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AS3711 − Register Over view
Figure 122:
Stepup_control4 Register (Address 53h)
Addr: 53h
Bit
7
6
Bit Name
stpup1_det
stpup1_oc
Stepup_control4
Default
0
0
Access
Bit Description
RO
SU1 detection status register
0 : VRsense < VDETECT for more than 1ms, and DCDC
SU1 converter is in pulseskip for more than 1ms.
1 : VRsense > VDETECT for more than 1ms, or the DCDC
SU1 converter is not in pulseskip for more than 1ms.
RO
SU1 overcurrent status bit
0 : VRsense < VOVCURRENT
1 : VRsense > VOVCURRENT for more than 5ms (latched
state)
5
stpup1_oc_timeout
0
RW
Controls GPIOx switch-OFF, after overcurrent timeout
(5ms) for DCDC SU1
0 : Disabled
1 : Enabled
4
stpup1_shortprot
0
RW
Enables Protection and Detection circuit for DCDC SU1
0 : No protection and load detection
1 : Short protection and load detection enabled
RW
Selects PWM operation of SU2
0 : High frequency operation PWM>20kHz**
1 : Low frequency PWM operation: stepup2_on and
curr1 to 3_on (if PWM enabled) switched OFF during
PWM low time
** Step_up switched ON all the time. (current sinks are
not switched OFF (currX_on=1 all the time), but
currX_current masked to 00h during PWM low time.).
During PWM OFF-time then feedback voltage is
sampled.
RW
DCDC SU2 overvoltage protection to prevent damage
of external NFET, if CURR1, CURR2 or CURR3 feedback
selected, and no LED string connected.
0 : Switch OFF DCDC SU2 if the voltage on FB_SU2
exceeds 1.25V
1 : Overvoltage protection disabled
RW
Controls the feedback source
0 : Voltage feedback (external resistor divider) selected
by stepup2_fbprot
1 : CURR1 feedback enabled (feedback through white
LEDs)
2 : CURR2 feedback enabled (feedback through white
LEDs)
3 : CURR3 feedback enabled (feedback through white
LEDs)
3
2
1:0
stpup2_pwm_lowf
stepup2_prot_dis
stepup2_fb
Page 110
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0
0
'b00
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 123:
Stepup_control5 Register (Address 54h)
Addr: 54h
Stepup_control5
Bit
Bit Name
Default
Access
Bit Description
7:4
-
'b0000
n/a
Do not use
3
stepup2_pwm_mode
0
RW
Enable PWM mode
0 : Normal operation
1 : PWM mode operation. Feedback is sampled
during PWM OFF-time, if stpup2_lowf=0.
2
stepup12_clkinv
0
RW
Invert input clock of SU1 and SU2 converter
0 : Use positive edge of internal clk
1 : Use negative edge of internal clk
RW
Controls the feedback protection of SU2 with
external resistor divider (regulated to 0.8V).
0 : LX_SD4 enabled as input (If SD4 not used)
1 : GPIO2 enabled as input
2 : GPIO3 enabled as input
3 : GPIO4 enabled as input
1:0
stepup2_fbprot
'b00
Figure 124:
RTCcontrol Register (Address 60h)
Addr: 60h
RTCcontrol
Bit
Bit Name
Default
Access
Bit Description
7:5
-
'b000
n/a
Do not use
4:3
rtc_irq_mode
'b00
RW
0 : Generates an interrupt every second
1 : Generates an interrupt every minute
2 : Generates an interrupt every 2 minute
3 : Generates an interrupt every 8 minute
2
rtc_on
0
RW
Switch ON the 32kHz RTC oscillator
0 : 32kHz oscillator disabled
1 : 32kHz oscillator enabled
1
rtc_alarm_wakeup_en
0
RW
0 : Disables RTC alarm wake-up in power OFF mode
1 : Enable RTC alarm wake-up in power OFF mode
RW
0 : Disables RTC repeated wake-up in power OFF
mode
1 : Enable RTC repeated wake-up in power OFF
mode
0
rtc_rep_wakeup_en
ams Datasheet
[v1-34] 2014-Nov-10
0
Page 111
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AS3711 − Register Over view
Figure 125:
RTCSecond Register (Address 61h)
Addr: 61h
RTCSecond
Bit
Bit Name
Default
Access
7:0
second
00h
RW
Bit Description
-
Figure 126:
RTCMinute1 Register (Address 62h)
Addr: 62h
RTCMinute1
Bit
Bit Name
Default
Access
7:0
minute0
00h
RW
Bit Description
-
Figure 127:
RTCMinute2 Register (Address 63h)
Addr: 63h
RTCMinute2
Bit
Bit Name
Default
Access
7:0
minute1
00h
RW
Bit Description
-
Figure 128:
RTCMinute3 Register (Address 64h)
Addr: 64h
RTCMinute3
Bit
Bit Name
Default
Access
7:0
minute2
00h
RW
Bit Description
-
Figure 129:
RTCAlarmSecond Register (Address 65h)
Addr: 65h
RTCAlarmSecond
Bit
Bit Name
Default
Access
Bit Description
7:0
alarmsecond
3Fh
RW
AlarmMinute2 has to be written to latch the whole
alarm register
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ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 130:
RTCAlarmMinute Register (Address 66h)
Addr: 66h
RTCAlarmMinute
Bit
Bit Name
Default
Access
Bit Description
7:0
alarmminute0
FFh
RW
AlarmMinute2 has to be written to latch the whole
alarm register
Figure 131:
RTCAlarmMinute2 Register (Address 67h)
Addr: 67h
RTCAlarmMinute2
Bit
Bit Name
Default
Access
Bit Description
7:0
alarmminute1
FFh
RW
AlarmMinute2 has to be written to latch the whole
alarm register
Figure 132:
RTCAlarmMinute3 Register (Address 68h)
Addr: 68h
RTCAlarmMinute3
Bit
Bit Name
Default
Access
7:0
alarmminute2
FFh
RW
Bit Description
-
Figure 133:
SRAM Register (Address 69h)
Addr: 69h
SRAM
Bit
Bit Name
Default
Access
7:0
SRAM
00h
RW
ams Datasheet
[v1-34] 2014-Nov-10
Bit Description
-
Page 113
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AS3711 − Register Over view
Figure 134:
ADC_control Register (Address 70h)
Addr: 70h
ADC_control
Bit
Bit Name
Default
Access
Bit Description
7
start_conversion
0
RW
Writing a 1 into this bit starts one ADC conversion
6
adc_on
0
RW
Writing a 1 into this bit continuously activates the
ADC S/H and the input multiplexer. The ADC and
the MUX are also activated for a conversion period
when start_conversion is set to 1. Useful for high
impedance input sources on ADC inputs
5
adc_slow
0
RW
Select ADC sampling frequency
0 : 250kHz (conversion time: approx. 60μs)
1 : 62.5kHz (conversion time:approx. 240μs)
RW
0 : High voltage range of GPIO1 to 4/SENSEN_SU1
(4:1 divider active)
1 : Low voltage range of GPIO1 to 4/SENSEN_SU1
(1:1 divider, 1.8V max)
RW
Selects an ADC channel
0 : BATTEMP NTCADCIN (1:1)
1 : Temperature sensor: DIE temperature [ºC] =
adc_result * 0.866 -274 (1:1)
2 : XOUT32K (1:1, 1.8Vmax)
3 : CURR1 (1:1, 1V max)
4 : CURR2 (1:1, 1V max)
5 : CURR3 (1:1, 1V max)
6 : VUSB(15:1, 15V max)
7 : CHGIN (4:1)
8 : VBAT (4:1)
9 : VSUP (4:1)
10 : SENSEN_SU1 (4:1 or 1:1 )
11 : LX_SD4 (4:1 or 1:1 )
12 : GPIO2 (4:1 or 1:1 )
13 : GPIO3 (4:1 or 1:1 )
14 : GPIO4 (4:1 or 1:1 )
15 : NA
4
3:0
gpio_lv
adc_select
Page 114
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0
'b0000
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 135:
ADC_MSB_result Register (Address 71h)
Addr: 71h
ADC_MSB_result
Bit
Bit Name
Default
Access
Bit Description
7
result_not_ready
0
RO
Indicates end of conversion 0 result is ready 1
conversion is running
6:0
D9_3
'b000 0000
RO
ADC result register Bit9 to Bit3
Figure 136:
ADC_LSB_result Register (Address 72h)
Addr: 72h
ADC_LSB_result
Bit
Bit Name
Default
Access
7:3
-
'b0000 0
n/a
Do not use
2:0
D2_0
'b000
RO
ADC result register Bit2 to Bit0
ams Datasheet
[v1-34] 2014-Nov-10
Bit Description
Page 115
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AS3711 − Register Over view
Figure 137:
RegStatus Register (Address 73h)
Addr: 73h
RegStatus
Bit
Bit Name
Default
Access
Bit Description
7
curr3_lv
0
RO
Bit is set when voltage of current sink CURR3 drops
below low voltage threshold (1ms debounce time
default)
6
curr2_lv
0
RO
Bit is set when voltage of current sink CURR2 drops
below low voltage threshold (1ms debounce time
default)
5
curr1_lv
0
RO
Bit is set when voltage of current sink CURR1 drops
below low voltage threshold (1ms debounce time
default)
4
-
0
n/a
Do not use
3
sd4_lv
0
RO
Bit is set when voltage of SD4 drops below low
voltage threshold (-5%) (1ms debounce time
default)
2
sd3_lv
0
RO
Bit is set when voltage of SD3 drops below low
voltage threshold (-5%) (1ms debounce time
default)
1
sd2_lv
0
RO
Bit is set when voltage of SD2 drops below low
voltage threshold (-5%) (1ms debounce time
default)
0
sd1_lv
0
RO
Bit is set when voltage of SD1 drops below low
voltage threshold (-5%) (1ms debounce time
default)
Page 116
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ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 138:
InterruptMask1 Register (Address 74h)
Addr: 74h
InterruptMask1
Bit
Bit Name
Default
Access
7
LowBat_int_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
6
ovtmp_int_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
5
onkey_int_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
4
chdet_int_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
3
eoc_int_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
2
resume_int_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
1
nobat_int_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
0
trickle_int_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
ams Datasheet
[v1-34] 2014-Nov-10
Bit Description
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AS3711 − Register Over view
Figure 139:
InterruptMask2 Register (Address 75h)
Addr: 75h
InterruptMask2
Bit
Bit Name
Default
Access
Bit Description
7
rtc_rep_int_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
6
stpup1_det_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
5
stpup1_oc_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
4
bat_temp_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
3
sd4_lv_int_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
2
sd3_lv_int_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
1
sd2_lv_int_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
0
sd1_lv_int_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
Figure 140:
InterruptMask3 Register (Address 76h)
Addr: 76h
InterruptMask3
Bit
Bit Name
Default
Access
7:3
-
'b0000 0
n/a
Do not use
2
gpio_restart_int_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
1
gpio_int_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
0
rtc_alarm_int_m
1
RW
0 : Interrupt enabled
1 : Interrupt masked (disabled)
Page 118
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Bit Description
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 141:
InterruptStatus1 Register (Address 77h)
Addr: 77h
InterruptStatus1
Bit
Bit Name
Default
Access
Bit Description
7
LowBat_int_i
0
POP
Bit is set when VSUP drops below ResVoltFall
6
ovtmp_int_i
0
POP
Bit is set when 110deg is exceeded
5
onkey_int_i
0
POP
Rising and falling edge
4
chdet_int_i
0
POP
Rising and falling edge
3
eoc_int_i
0
POP
Rising and falling edge
2
resume_int_i
0
POP
Rising and falling edge
1
nobat_int_i
0
POP
Rising and falling edge
0
trickle_int_i
0
POP
Rising and falling edge
Figure 142:
InterruptStatus2 Register (Address 78h)
Addr: 78h
InterruptStatus2
Bit
Bit Name
Default
Access
7
rtc_rep_int_i
0
POP
Rising edge only
6
stpup1_det_i
0
POP
Rising edge only
5
stpup1_oc_i
0
POP
Rising edge only
4
bat_temp_i
0
POP
Rising and falling edge
3
sd4_lv_int_i
0
POP
Rising edge only
2
sd3_lv_int_i
0
POP
Rising edge only
1
sd2_lv_int_i
0
POP
Rising edge only
0
sd1_lv_int_i
0
POP
Rising edge only
ams Datasheet
[v1-34] 2014-Nov-10
Bit Description
Page 119
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AS3711 − Register Over view
Figure 143:
InterruptStatus3 Register (Address 79h)
Addr: 79h
InterruptStatus3
Bit
Bit Name
Default
Access
7:3
-
'b0000 0
n/a
Do not use
2
gpio_restart_int_i
0
POP
Falling edge
1
gpio_int_i
0
POP
Rising and falling edge
0
rtc_alarm_int_i
0
POP
Rising edge only
Page 120
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Bit Description
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 144:
ChargerControl1 Register (Address 80h)
Addr: 80h
ChargerControl1
Bit
Bit Name
Default
Access
7
nobat_ntc_det
1
RW
Enables nobat_det feature with NTC, ntc_nobat
debounce time=100ms
RW
0 : Charger will stay in EOC even when the battery
voltage drops
1 : Charger will start charging when the battery
voltage hits the resume level
RW
0 : USB is supplying VSUP, but battery switch is
open. USB charger regulates to Vsup_voltage
1 : Normal battery charger operation form USB
charger
RW
Sets the USB input current limit, if not GPIO
controlled
0 : 94mA (USB low current, also if gpiox_iosf=12
and gpiox=0)
1 : 141mA
2 : 189mA
3 : 237mA
4 : 285mA
5 : 332mA
6 : 380mA
7 : 428mA
8 : 470mA (USB high current, also if gpiox_iosf=12
and gpiox=1)
9 : 517mA
10 : 754A
11 : 1.29A
12 : 1.7A
13 : 2.53A
14 : 2.53A
15 : 2.53A
RW
ON/OFF control of USB charger input current
limiter
0 : Input current limiter disabled
1 : Input current limiter enabled
6
5
4:1
0
auto_resume
bat_charging_enable
usb_current
usb_chgEn
ams Datasheet
[v1-34] 2014-Nov-10
1
0
'b1000
1
Bit Description
Page 121
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AS3711 − Register Over view
Figure 145:
ChargerVoltageControl Register (Address 81h)
Addr: 81h
Bit
7:6
5:0
Bit Name
vsup_min
ChVoltEOC
Page 122
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ChargerVoltageControl
Default
'b01
'b10 0011
Access
Bit Description
RW
Regulate down battery charging current on that
level of VSUP during trickle charging and constant
current charging, to prevent voltage drop on VSUP.
0 : 3.9V
1 : 4.2V
2 : 4.50V
3 : 4.70V
RW
Sets the end-of-charge voltage level VCHOFF (20mV
steps)
0 : 3.5V
1 : 3.52V
... : ...
35 : 4.2V
... : ...
47-63 : 4.44V
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 146:
ChargerCurrentControl Register (Address 82h)
Addr: 82h
ChargerCurrentControl
Bit
Bit Name
Default
Access
7
eoc_current
0
RW
Sets eoc_current
0 : eoc current = TrickleCurrent
1 : eoc current = TrickleCurrent / 2
RW
Sets the range of the charging current limit in
constant current mode.
0 : Normal mode
1 : Low current mode Current= ConstantCurrent
-500mA
RW
Sets the charging current limit in constant current
mode.
0 : 750mA
1 : 800mA
2 : 850mA
3 : 900mA
4 : 950mA
5 : 1000mA
6 : 1050mA
7 : 1100mA
8 : 1150mA
9 : 1200mA
10 : 1250mA
11 : 1300mA
12 : 1350mA
13 : 1400mA
14 : 1450mA
15 : 1500mA
RW
Sets the charging current limit in trickle current
mode.
0 : 60mA
1 : 120mA
2 : 180mA
3 : 240mA
6
5:2
1:0
cc_lowlimit
ConstantCurrent
TrickleCurrent
ams Datasheet
[v1-34] 2014-Nov-10
1
'b0000
'b01
Bit Description
Page 123
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AS3711 − Register Over view
Figure 147:
ChargerConfig Register (Address 83h)
Addr: 83h
ChargerConfig
Bit
Bit Name
Default
Access
Bit Description
7
-
0
n/a
Do not use
6
Charging_1Hz_clk
0
RW
Sets the mode for the charging output status
(gpioX_iosf=10)
0 : Normal operation: charging=1, not charging=0
1 : 1Hz blinking operation: charging=1Hz, not
charging=0
5
ChVoltResume
0
RW
Sets the resume voltage level VCHRES.
0 : 120mV
1 : 240mV
RW
Selects temperature regulation of charging current
(die temperature)
0 : 110°C
1 : 90°C
2 : 120°C
3 : 130°C
RW
Voltage regulation of VSUP of the input current
limiter
0 : 4.4V
1 : 4.5V
2 : 4.6V
3 : 4.7V
4 : 4.8V
5 : 4.9V
6 : 5.0V
7 : 5.5V
4:3
2:0
temp_sel
vsup_voltage
Page 124
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'b00
'b101
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 148:
NTCsupervision Register (Address 84h)
Addr: 84h
NTCsupervision
Bit
Bit Name
Default
Access
7:3
-
'b0000 0
n/a
Do not use
2
ntc_temp
0
RW
Select NTC mode
0 : 50deg temperature limit
1 : 45deg temperature limit
1
ntc_10k
0
RW
Select NTC resistor type
0 : 100kΩ
1 : 10kΩ
0
ntc_on
0
RW
ON/OFF control of battery NTC supervision
0 : Disabled
1 : Enabled
ams Datasheet
[v1-34] 2014-Nov-10
Bit Description
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AS3711 − Register Over view
Figure 149:
Chargersupervision Register (Address 85h)
Addr: 85h
Chargersupervision
Bit
Bit Name
Default
Access
Bit Description
7
-
0
n/a
Do not use
6
ovprot_dis
0
RW
Disables external overvoltage protection, function of XOFF
pin
0 : Overvoltage protection enabled
1 : Overvoltage protection disabled
5
dcdc_chmode
1
RW
Enables DCDC charger mode
0 : Linear charger mode enabled
1 : Step down charger enabled
4
charging_tmax
1
RW
0 : Read: no time-out reached, Write: reset charger time-out
counter
1 : ch_timeout reached and charging stopped
RW
Sets the charger time-out timer
0 : OFF
1 : 0.5 hour
2 : 1 hour
3 : 1.5 hour
4 : 2 hour
5 : 2.5 hour
6 : 3 hour
7 : 3.5 hour
8 : 4 hour
9 : 4.5 hour
10 : 5 hour
11 : 5.5 hour
12 : 6 hour
13 : 6.5 hour
14 : 7 hour
15 : 7.5 hour
3:0
ch_timeout
Page 126
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'b0000
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Register Overview
Figure 150:
ChargerStatus1 Register (Address 86h)
Addr: 86h
ChargerStatus1
Bit
Bit Name
Default
Access
Bit Description
7
Nobat
0
RO
Bit is set, if no battery has been detected (after EOC
measured on NTC)
6
Battemp_hi
0
RO
Bit is set, if high battery temperature has been
detected
5
EOC
0
RO
Bit is set, if End of charge state has been reached
4
CVM
0
RO
Bit is set, if charger is operating in constant voltage
mode
3
Trickle
0
RO
Bit is set, if charger is operating in trickle current.
VBAT < 2.9V
2
Resume
0
RO
Bit is set, if Battery voltage is below resume level
1
CCM
0
RO
Bit is set, if charger is operating in constant current
mode
0
ChDet
0
RO
Bit is set when external charge adapter has been
detected on pin VCHARGER
Figure 151:
ChargerStatus2 Register (Address 87h)
Addr: 87h
ChargerStatus2
Bit
Bit Name
Default
Access
7:3
-
‘b0000 0
n/a
Do not use
Bit indicates, that the USB input voltage protection
pin XOFF is precharged to a voltage > 7.5V XOFF is
pull to GND if an overvoltage on VUSB is detected.
2
usb_prot_ready
0
RO
1
batsw_on
0
RO
0
batsw_mode
0
RO
ams Datasheet
[v1-34] 2014-Nov-10
Bit Description
Bits indicates the status of the battery switch
00 : Battery switch closed
01 : Battery switch open with ideal diode
10 : Charging mode
11 : Battery switch closed
Page 127
Document Feedback
AS3711 − Register Over view
Figure 152:
Lock Register (Address 8eh)
Addr: 8eh
Lock
Bit
Bit Name
Default
Access
7:3
-
‘b0000 0
n/a
Do not use
RW
Enables lock of the following charger registers: 81h,
82h, 83h, Chargervoltagecontrol,
Chargercurrentcontrol, Chargerconfig.
Bits can only be set. Reset only with full reset cycle
RW
Enables lock of Regulator voltages Bits can only be
set. Reset only with full reset cycle
0 : No lock
1 : Lock of voltage of LDOs (LDO1..8_vsel) (all bits)
and voltage of StepDownBits(sd1..4_vsel) [5:6] only
2 : Lock voltage of StepDownbits 5:6 only (no LDOs)
3 : Lock voltage of StepDowns (all bits) and LDOs
(all bits).
Note: Setting sdx_vsel to 0 is possible all the time
to allow switching OFF the regulator. Writing
a non-zero value after that will restore the
old value.
Bit Description
2
1:0
charger_lock
0
reg_lock
'b00
Bit Description
Figure 153:
ASIC_ID1 Register (Address 90h)
Addr: 90h
ASIC_ID1
Bit
Bit Name
Default
Access
7:0
ID1
8Bh
RO
-
Figure 154:
ASIC_ID2 Register (Address 91h)
Addr: 91h
ASIC_ID2
Bit
Bit Name
Default
Access
3:0
revision
'b0001
RO
Page 128
Document Feedback
Bit Description
For chip version 2v1 (metal fuse)
ams Datasheet
[v1-34] 2014-Nov-10
1
3
5
1
3
5
J5
2
4
6
BU4
GND
R16
1M
BU3
VBAT
2.2uF
10uF
47uF
C41
C19
1
U2
5
4
3
2
I2C
2
4
6
100nF
C28
Q2
VSUP
BU2
C24
GND
Shield
BUS_GND
D+
D-
BUS_PWR
C15
R17
10k
S1
D1
1μH
L3
RESET
R15
10k
ON
BATTEMP
VSUP
C13
4.7uF
10uF
C23
4.7uF
Q1
S2
C29
1
Q5
D4
1uF
R9
1k
VSUP
Y1
57
25
24
23
22
38
39
37
36
40
5
34
4
1
3
2
35
2.2uF
VSS(exp)
XRES
SDA
SCL
ON
XOUT32
XIN32
V2_5
CREF
BATTEMP
CHGOUT
VBAT
VSUP_CHG
EXTBATSW
CHGIN
XOFF
VUSB
2.2uF
C9 C10 C11
2.2uF
VSUP
31
56
18
AS3711
VIN_LDO123
VIN_LDO456
VIN_LDO78
CURR1
CURR2
CURR3
BU1
3
2
GPIO1
GPIO2
GPIO3
GPIO4
VSUP_GPIO
D6
D7
C17
26
27
28
29
21
GPIO1
GPIO2
GPIO3
GPIO4
15
16
17
CURR1
CURR2
CURR3
32
30
33
55
54
53
20
19
LDO1
LDO2
LDO3
LDO4
LDO5
LDO6
LDO7
LDO8
VSUP_SU
45
C8
C3
C4
C5
C6
C7
C1
D8
2.2uF
VSUP
D9
FB_SD4
NGATE_SD4
LX_SD4
PGATE_SD4
SENSEN_SD4
GATE_SU2
SENSEN_SU2
FB_SU1
GATE_SU1
SENSEN_SU1
FB_SD1
LX_SD1
FB_SD2
LX_SD2
FB_SD3
LX_SD3
VSUP_SD1
VSUP_SD2
VSUP_SD3
46
42
43
44
41
49
51
52
48
47
12
13
9
10
8
7
14
11
6
1μH
1μH
L2
L4
1
Q6
3
1μH
L7
1.5μH
4
6
C35
2.2uF
33m VSUP
R19
C25
10μF
SD3
*
SD1
10μH
L6
4.7μH L5
Project Title
150m
R7
VSUP
150m
R4
C14
10μF
Date 01/06/2011
Originator *
Size
A4
Title
C36
33uF
SD4
SD2
C20
10μF
C21
2.2uF
VSUP
C16
2.2uF
LDO1
LDO2
LDO3
LDO4
LDO5
LDO6
LDO7
LDO8
2.2uF
C12
2.2uF
L1
1uF 1uF 2.2uF 2.2uF 2.2uF 1uF 2.2uF
C2
SENSEP
50
2
5
1
Q4
1
Q3
2.2uF
C22
VSUP
3
2.2uF
C31
2
3
ams Datasheet
[v1-34] 2014-Nov-10
2
VUSB
D3
D2
C34
SU1
C33
2.2uF
SU2
C27
10uF
of
*
Revision
*
15nF
Sheet *
R14
100k
1M
R11 1.5nF
C32
C30
33nF
330k
15nF
C26
R8
1M
R6
AS3711 − Application Information
Application Information
Figure 155:
AS3711 Application Schematic
Page 129
Document Feedback
AS3711 − Application Information
Figure 156:
PCB Layout Recommendation for SD1, SD2, SD3 and Switched Mode Charger
Page 130
Document Feedback
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Application Information
Figure 157:
PCB Layout Recommendation for SU1, SU2, SD4
ams Datasheet
[v1-34] 2014-Nov-10
Page 131
Document Feedback
AS3711 − Package Drawings & Mark ings
Package Drawings & Markings
Figure 158:
Package Drawings and Dimensions QFN56
Symbol
Min
Nom
Max
A
0.80
0.90
1.00
A1
0
0.02
0.05
A2
-
0.65
1.00
A3
-
0.20REF
-
L
0.35
0.40
0.45
Θ
0°
-
14°
b
0.15
0.20
0.25
D
7.00BSC
E
7.00BSC
e
0.40BSC
D2
4.90
5.00
5.10
E2
4.90
5.00
5.10
D1
-
6.75BSC
-
E1
-
6.75BSC
-
aaa
-
0.10
-
bbb
-
0.07
-
ccc
-
0.10
-
ddd
-
0.05
-
eee
-
0.08
-
fff
-
0.10
-
N
RoHS
56
Green
Note(s) and/or Footnote(s):
1. Dimensions and tolerancing confirm to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. Coplanarity applies to the exposed heat slug as well the terminal.
4. Radius on the terminal is optional.
5. N is the total number of the terminal.
Page 132
Document Feedback
ams Datasheet
[v1-34] 2014-Nov-10
A S 3 7 1 1 − Package Drawings & Markings
Figure 159:
Package Drawings and Dimensions CSP64
RoHS
Green
Note(s) and/or Footnote(s):
1. Pin 1 = A1
2. ccc Coplanarity
3. All dimensions are in μm
ams Datasheet
[v1-34] 2014-Nov-10
Page 133
Document Feedback
AS3711 − Package Drawings & Mark ings
Figure 160:
Marking
YYWWIZZ
AS3711 @
M2V1-xx
Figure 161:
Package Code YYWWIZZ
YY
WW
I
ZZ
@
Year
Working week assembly / packaging
Plant identifier
Free choice
Sublot Identifier
(for QFN only)
Figure 162:
Start-up Revision Code
xx
Sequence
FF
Engineering samples, no sequence programmed or sequence programmed on request
00
Default sequence (no sequence programmed)
xx
Customer specified sequence programmed during production test
Page 134
Document Feedback
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Ordering & Contact Information
Ordering & Contact Information
The devices shown in Figure 163 are available as standard
products.
Figure 163:
Ordering Information
Part Number
Marking
Sequence
Description
Delivery
Form
Package
AS3711-BQFR-FF
M2V1-FF
Sequence
programmable on
request
Quad Buck High Current
PMIC with Charger
Tape & Reel
dry pack
QFN56 7×7
0.4mm pitch
AS3711-BQFP-00
M2V1-00
Default sequence
Quad Buck High Current
PMIC with Charger
Tape & Reel
dry pack
QFN56 7×7
0.4mm pitch
AS3711-BQFP-xx
M2V1-xx
Customer specified
Quad Buck High Current
PMIC with Charger
Tape & Reel
dry pack
QFN56 7×7
0.4mm pitch
AS3711-BWLT-FF
M2V1-FF
Sequence
programmable on
request
Quad Buck High Current
PMIC with Charger
Tape & Reel
WL-CSP64,
0.4mm pitch
AS3711-BWLT-00
M2V1-00
Default sequence
Quad Buck High Current
PMIC with Charger
Tape & Reel
WL-CSP64,
0.4mm pitch
AS3711-BWLT-xx
M2V1-xx
Customer specified
Quad Buck High Current
PMIC with Charger
Tape & Reel
WL-CSP64,
0.4mm pitch
Buy our products or get free samples online at:
www.ams.com/ICdirect
Technical Support is available at:
www.ams.com/Technical-Support
Provide feedback about this document at:
www.ams.com/Document-Feedback
For further information and requests, e-mail us at:
ams_sales@ams.com
For sales offices, distributors and representatives, please visit:
www.ams.com/contact
Headquarters
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
ams Datasheet
[v1-34] 2014-Nov-10
Page 135
Document Feedback
AS3711 − RoHS Compliant & ams Green Statement
RoHS Compliant & ams Green
Statement
RoHS: The term RoHS compliant means that ams AG products
fully comply with current RoHS directives. Our semiconductor
products do not contain any chemicals for all 6 substance
categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, RoHS compliant products are
suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br): ams Green
defines that in addition to RoHS compliance, our products are
free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous
material).
Important Information: The information provided in this
statement represents ams AG knowledge and belief as of the
date that it is provided. ams AG bases its knowledge and belief
on information provided by third parties, and makes no
representation or warranty as to the accuracy of such
information. Efforts are underway to better integrate
information from third parties. ams AG has taken and continues
to take reasonable steps to provide representative and accurate
information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. ams AG
and ams AG suppliers consider certain information to be
proprietary, and thus CAS numbers and other limited
information may not be available for release.
Page 136
Document Feedback
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Copyrights & Disclaimer
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141
Unterpremstaetten, Austria-Europe. Trademarks Registered. All
rights reserved. The material herein may not be reproduced,
adapted, merged, translated, stored, or used without the prior
written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent
indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied,
or by description regarding the information set forth herein.
ams AG reserves the right to change specifications and prices
at any time and without notice. Therefore, prior to designing
this product into a system, it is necessary to check with ams AG
for current information. This product is intended for use in
commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or
high reliability applications, such as military, medical
life-support or life-sustaining equipment are specifically not
recommended without additional processing by ams AG for
each application. This product is provided by ams AG “AS IS”
and any express or implied warranties, including, but not
limited to the implied warranties of merchantability and fitness
for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out
of ams AG rendering of technical or other services.
ams Datasheet
[v1-34] 2014-Nov-10
Page 137
Document Feedback
AS3711 − Document Status
Document Status
Document Status
Product Preview
Preliminary Datasheet
Datasheet
Datasheet (discontinued)
Page 138
Document Feedback
Product Status
Definition
Pre-Development
Information in this datasheet is based on product ideas in
the planning phase of development. All specifications are
design goals without any warranty and are subject to
change without notice
Pre-Production
Information in this datasheet is based on products in the
design, validation or qualification phase of development.
The performance and parameters shown in this document
are preliminary without any warranty and are subject to
change without notice
Production
Information in this datasheet is based on products in
ramp-up to full production or full production which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade
Discontinued
Information in this datasheet is based on products which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and
should not be used for new designs
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Revision Information
Revision Information
Changes from 1.2 (2012-May) to current revision 1-34 (2014-Nov-10)
Page
Content of austriamicrosystems datasheet was updated to latest ams design
Added CSP package information to the datasheet
Added benefits and CSP package to Figure 1
2
Updated QFN blockdiagram (Figure 2)
4
Added CSP block diagram (Figure 3)
5
Added Ball Assignment CSP (Figure 5)
7
Added CSP ball info. and updated pins VINLDO78, XRES, VINLDO456 & VSSA (Figure 6)
7
Updated Figure 7
11
Added Cload_LDO3-8_L & Cload_LDO3-8_H parameters to Figure 28
29
Added Iout to Figure 29
31
Updated text under DCDC Step-Up Converter
32
Renamed VFB2 to VCURR in Figure 35
38
Updated ICURR1,2,3 in Figure 39 and text under Current Sinks
40
Updated text under Charger
41
Updated text under NTC supervision
45
Updated Figure 51
53
Renamed VXRES to VRES in Figure 52
54
Updated Figure 54
57
Updated descriptions of IO Functions
59
Updated sections Vselect Input & Stand-by and Vselect input
60
Updated Figure 62
67
Updated description of Real Time Clock
69
Replaced osc_pd=1with rtc_on=0 in GPIO1-,GPIO2-,GPIO3-, GPIO4- control registers
Replaced osc_pd=1with rtc_on=0 in curr_control register
Changed 0.15mA to 0.1562mA and 38.25 to 39.84 in curr1-,curr2-, curr3_value registers
Updated bit 6 in Chargersupervision register
ams Datasheet
[v1-34] 2014-Nov-10
86 - 89
105
106 - 107
126
Page 139
Document Feedback
AS3711 − Revision Information
Changes from 1.2 (2012-May) to current revision 1-34 (2014-Nov-10)
Page
Updated ASIC_ID2 Register
128
Updated Figure 159
133
Updated Figure 160 & Figure 161
134
Updated Figure 163
135
Note(s) and/or Footnote(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.
Page 140
Document Feedback
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Content Guide
Content Guide
1
2
3
General Description
Key Benefits & Features
Applications
6
11
13
14
Pin Assignments
Absolute Maximum Ratings
Electrical Characteristics
Typical Operation Characteristics
15
Detailed Description - Power Management
Functions
DCDC Step-Down Converter
Description
Mode Settings
Low ripple, low noise operation:
High efficiency operation (default setting):
Low power mode operation (automatically controlled):
DVM (Dynamic Voltage Management)
Fast Regulation Mode
Selectable Frequency Operation
100% PMOS ON Mode for Low Dropout Regulation
Step-Down Converter Configuration Modes
Parameter
DCDC Step-Down Controller
Description
Parameter
Analog LDO Regulators
Description
Parameter
Digital LDO Regulators
Description
Parameter
Low power LDO V2_5 Regulators
Description
Parameter
DCDC Step-Up Converter
Description
Feedback selection SU1
Feedback Selection SU2
Current Feedback
Current Feedback with Automatic Feedback Selection
Voltage Feedback
Calculating Resistors for Voltage Feedback or Over-Voltage Protection
Output Disconnect
StepUp1 Load Detection and Over-current Protection
Circuit
Parameter
Current Sinks
Description
Parameter
Charger
Description
Charging Cycle Description
15
15
16
16
16
17
18
18
18
18
18
20
23
23
24
27
27
28
29
29
29
31
31
31
32
32
34
34
34
34
34
34
35
36
38
40
40
40
41
41
42
ams Datasheet
[v1-34] 2014-Nov-10
Page 141
Document Feedback
AS3711 − Content Guide
42
42
42
43
43
44
44
45
Page 142
Document Feedback
45
45
46
47
48
Charge adapter detection
Soft charging
Low current (trickle) charging
Constant current charging
Constant voltage charging
Charger States
Stop charging conditions
Battery presence indication and operation without battery
Charger overvoltage protection
NTC supervision
Charger Modes
Alternative Charger Input Configurations
Parameter
52
52
53
53
53
54
54
54
54
55
56
56
56
56
56
56
57
57
58
58
58
59
59
59
59
59
60
60
60
60
60
61
61
61
61
61
61
61
61
Detailed Description - System Functions
Start-up
Normal Startup
Startup from Charger
Parameter
Reset
Description
Parameter
Reset Conditions
Voltage Detection:
Power OFF:
Software forced reset
External triggered reset:
Over-temperature reset:
Watchdog reset:
Long ON-key press:
Stand-by
Description
Internal References
Low Power Mode
Parameter
GPIO Pins
Description
IO Functions
Normal IO operation:
Interrupt output:
VSUP_low output
GPIO interrupt input
Current sink PWM input
Vselect input
Stand-by and Vselect input
PWRGOOD output
Q32k output
Watchdog input
SU1 OC output
Charger active output
EOC output
100/500mA charger input
500/2.5A charger input
ams Datasheet
[v1-34] 2014-Nov-10
AS3711 − Content Guide
ams Datasheet
[v1-34] 2014-Nov-10
61
62
62
63
63
64
64
64
65
65
66
66
67
69
69
69
70
70
70
74
Charging enable input
PWM output
Parameter
Supervisor
Description
Watchdog
Description
Parameter
Interrupt Generation
Description
10-Bit ADC
Input Sources
Parameter
Real Time Clock
Description
Alarm
2-Wire-Serial Control Interface
Feature List
Protocol
Parameter
75
129
132
135
136
137
138
139
Register Overview
Application Information
Package Drawings & Markings
Ordering & Contact Information
RoHS Compliant & ams Green Statement
Copyrights & Disclaimer
Document Status
Revision Information
Page 143
Document Feedback
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